The present application relates to manufacturing of semiconductor integrated circuits, and more particularly to formation of field effect transistor (FET) devices in such integrated circuits. Continued innovations in semiconductor process technologies are enabling higher integration densities and associated device scaling. As the semiconductor industry moves towards the 7 nm production node and beyond, FET devices must be scaled to smaller dimensions to provide an increased effective channel width per footprint area. Such scaling in some cases is achieved using nanosheet FET devices. A given nanosheet FET device comprises a channel which includes multiple nanosheet layers arranged in a stacked configuration, with each such nanosheet layer having a vertical thickness that is substantially less than its width. A common gate structure is formed in areas above and below the nanosheet layers in the stacked configuration, thereby increasing the effective channel width of the resulting device, and thus the drive current it can support, for a given footprint area. Nanosheet technologies are considered to be a viable option for continued scaling of metal-oxide-semiconductor (MOS) devices, such as complementary MOS (CMOS) devices each comprising an N-type FET (NFET) and a P-type FET (PFET). However, problems can arise in conjunction with lithographic patterning of nanosheet device features at production nodes below 10 nm. For example, in patterning work function metal (WFM) portions of nanosheet FET devices in conjunction with replacement metal gate (RMG) formation, etching operations applied to release nanosheet layers of an NFET device channel structure can lead a severe undercut of a portion of the WFM of a corresponding adjacent PFET device channel structure, and vice-versa. A need therefore exists for techniques for alleviating such drawbacks in the formation of nanosheet FET devices.